1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to improvement of bit line precharge voltage in a dynamic semiconductor memory device.
2. Description of the Related Art
FIG. 4 is a block diagram illustrating an example of constitution of a dynamic semiconductor memory device (hereinafter referred to as "DRAM") in the prior art. Referring to FIG. 4, in a memory cell array 101, a plurality of word lines (not shown) and a plurality of bit lines (not shown) are arranged so as to intersect to each other, and a memory cell (not shown) is installed to each intersection point between these word lines and bit lines. In accordance with address signals AD from a microprocessor 100, selection of the memory cell is performed in every intersection point between one word line selected by an X address buffer decoder 102 and one bit line selected by a Y address buffer decoder 103. Data is written in the selected memory cell or data held in the memory cell is read out, and command of write/read of the data is performed by read/write control signal (R/W) supplied to an R/W control circuit 104 from the microprocessor 100. During the data write state, input data (Din) is input to the memory cell selected through the R/W control circuit 104. On the other hand, during the data read state, data held in the selected memory cell is detected and then amplified by a sense amplifier 105, and outputted as output data (Dout) through a data output buffer 106 to the outside.
FIG. 5 shows a portion of a set of bit line pairs in a dynamic semiconductor memory device in the prior art, for example, disclosed in "A 288K CMOS Pseudostatic RAM" IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, pp. 619-623, October 1984.
In FIG. 5, a plurality of word lines WL are arranged so as to intersect bit line pair BL, BL, and a memory cell MC is installed at an intersection point between each bit line BL or BL and each word line WL. In FIG. 5, only one memory cell MC connected to the bit line BL and one memory cell MC connected to the bit line BL are shown, and other memory cells are omitted. Each memory cell MC comprises a transfer transistor Qs and a storage capacitor C. The transistor Qs is connected between the bit line BL or BL and the storage capacitor C, and its gate is connected to the word line WL.
An N type sense amplifier NSA and a P type sense amplifier PSA are connected to the bit line pair BL, BL. The N type sense amplifier NSA comprises N-channel MOS transistor Q1 and Q2. The transistor Q1 is connected between the bit line BL and a node N1, and its gate is connected to the bit line BL. The transistor Q2 is connected between the bit line BL and the node N1, and its gate is connected to the bit line BL. The node N1 is connected through N-channel MOS transistor Q3 to the ground potential, and sense amplifier activating signal .phi.S.sub.N is supplied to the gate of the transistor Q3. The P type sense amplifier PSA comprises P-channel MOS transistors Q4 and Q5. The transistor Q4 is connected between the bit line BL and a node N2, and its gate is connected to the bit line BL. The transistor Q5 is connected between the bit line BL and a node N2, and its gate is connected to the bit line BL. The node N2 is connected through P-channel MOS transistor Q6 to the power source potential Vcc, and sense amplifier activating signal .phi.S.sub.P is supplied to gate of the transistor Q6. Further, an equalizing N-channel MOS transistor Q7 is connected between the bit line pair BL, BL, and its gate is supplied with equalizing signal BLEQ. Ends of the bit lines BL and BL are connected respectively through N-channel transistors Q8 and Q9 to input/output lines I/O, I/O and column selective signal Y is supplied to gate of the transistors Q8 and Q9.
Operation of the circuit in FIG. 5 will be described using an operation waveform chart in FIG. 6. When row address strobe signal RAS is at a logical high level or "H" level, i.e., in an off-time period, the sense amplifier activating signal .phi.S.sub.N attains the "H" level and the sense amplifier activating signal .phi.S.sub.P attains a logical low level or "L" level, and the sense amplifier NSA and PSA attain the active state. Thereby one potential of the bit line pair BL, BL is held to the "H" level, and other potential thereof is held to the "L" level. Next, when the row address strobe signal RAS is held at the "L" level, i.e., in an active period, first, the sense amplifier activating signal .phi.S.sub.N is made the "L" level and the sense amplifier activating signal .phi.S.sub.P is made the "H" level, thereby the sense amplifiers NSA and PSA are made non-active state. And then the equalizing signal BLEQ is once made the "H" level, and the bit line pair BL, BL is shortcircuited therebetween. Thereby potential of the bit lines BL and BL becomes intermediate potential (precharge potential) between the "H" level and the "L" level. After the equalizing signal BLEQ is returned to the "L" level and the shortcircuit of the bit line pair is released, word line drive signals .phi.WL rises to the power source potential Vcc (shown by solid line in FIG. 6). Thereby information, i.e., charge on the memory cell MC with the gate of its transistor connected to the selected word line WL is read out to the corresponding bit line BL or BL, and potential of the bit line BL or BL slightly rises or falls in accordance with the information of the memory cell MC. The potential of the bit line BL or BL not connected to the selected memory cell MC is still held to the precharge potential. Subsequently if the sense amplifier activating signal .phi.S.sub.N is made the "H" level and the sense amplifier activating signal .phi.S.sub.P is made the "L" level and the sense amplifiers NSA and PSA are made active, potential between the bit line BL and the bit line BL is amplified. As a result, between the bit line pair BL, BL, one line having higher potential is fixed to the "H" level, and other line having lower potential is fixed to the "L" level. Subsequently if column selective signal Y goes to the "H" level, the transistors Q8 ad Q9 are turned on, and potential of the bit line pair BL, BL is read out at the input/output lines I/O, I/O and the information is output. Subsequently if the row address strobe signal RAS rises to the "H" level, the active period ends and the word line drive signal WL falls to the "L" level. Thereby the transistor Qs of the memory cell MC with gate of its transistor connected to the selected word line WL is turned off. However, the sense amplifiers NSA and PSA are still held in the activated state before next active period begins. IF the row address strobe signal RAS becomes the "L" level and the active period begins, the above-mentioned operation is performed again.
FIG. 7 shows an equivalent circuit which takes out one of the memory cells shown in FIG. 5, and FIG. 8 shows characteristics of potential of the transistor of the memory cell explaining the potential holding operation of the memory cell in FIG. 9.
The operation characteristics will now be described referring to FIGS. 7 and 8.
Assume that potential applied to gate of the transistor Qs is V.sub.G, potential of the bit line BL being at the "H" Level is the power source potential Vcc, and potential held in the capacitor C is Vo. The transistor Qs is N-channel MOS transistor, and its threshold voltage is made V.sub.TM. In general, the gate potential V.sub.G attains to the power source potential Vcc at the "H" level state. In FIG. 8, the gate potential V.sub.G is taken on abscissa and the stored potential Vo of the capacitor C is taken on ordinate. In this case, the power source potential Vcc is made constant. First, the process will be described where the bit line BL is held to the power source potential Vcc, and selection of the word line, i.e., the gate potential V.sub.G rises to the power source potential Vcc. As shown in FIG. 8, when the gate potential V.sub.G becomes equal to the threshold voltage V.sub.TM of the transistor Qs, the transistor Qs begins to be turned on. Subsequently as the gate potential V.sub.G rises, the potential Vo held to the capacitor C also rises. When the gate potential V.sub.G reaches the power source potential Vcc, despite the potential Vcc of the bit line BL, the stored potential Vo of the capacitor C does not become the power source potential Vcc. That is, from characteristics of the N-channel transistor, the stored potential Vo at that time is Vcc--V.sub.TM (refer to point "X"). Consequently, when the power source potential Vcc is applied to the gate potential V.sub.G, the stored potential Vo of the capacitor C becomes lower than the power source potential Vcc appearing at the bit line BL by the threshold value of the transistor Qs.
FIG. 9 is a diagram illustrating potential around the memory cell in the prior art.
In FIG. 9, electronic potential 10 is shown as 5 regarding a storage node and as 6 regarding a bit line of a memory cell separated by the word line shown as 8. When information in the memory cell, i.e., stored potential is readout at the bit line, potential of the bit line 6 is already precharged to 1/2 Vcc. If information of the "H" level is held in the memory cell then, as above described, the stored potential is not the power source potential Vcc but Vcc-V.sub.TM. On the other hand, when the information charge held in the memory cell is at the "L" level, the potential held therein is 0V (Vss). Thus information at either the "H" level or the "L" level is held in the memory cell. In this case, taking the stored potentials at the "H" level and the "L" level as a basis, the precharge potential 1/2 Vcc of the bit line 6 is not in the intermediate position between these potential levels. That is, in FIG. 9, voltage A of difference between the potential held to the "L" level and the potential of 1/2 Vcc is 1/2 Vcc. On the contrary, voltage B of difference between the potential (Vcc-V.sub.TM) held in the memory cell of the "H" level and the potential of 1/2 Vcc is 1/2 Vcc-V.sub.TM. As a result, difference of the read-out voltages based on the precharge potential at the "H" level and the "L" level is not equal.
A system of this type wherein potential of the word line is raised to the power source potential Vcc is called a non-boost word line system.
In order to make difference of the read-out voltage equal as an improvement on the non-boost word line system as above described, a boost word line system has been employed in recent years. That is, as shown in broken line of FIG. 6, potential of the "H" level of the word line drive signal .phi.WL is raised above the power source potential Vcc further by the threshold voltage V.sub.TM of the transistor Qs.
FIG. 10 is a diagram illustrating potential around the memory cell in a boost word line system in the prior art.
In FIG. 10, the precharge potential 1/2 Vcc of the bit line 6 is similar to that of FIG. 9. However, if the gate potential V.sub.G of the transistor Qs in FIG. 6 is raised to Vcc+V.sub.TM, since the power source voltage Vcc of the bit line BL is transmitted as it is, the holding potential Vo held in the capacitor C becomes Vcc (refer to point "Y"). In this case, as shown in FIG. 9, the stored potential at "H" level of the storage node 5 of the memory cell becomes Vcc, and decrease of the potential by the threshold voltage of the transistor Qs is not produced. Consequently, the precharge potential 1/2 Vcc is in the intermediate position between "H" level and "L" level of the holding potential, and the read-out voltages A and B based on the precharge potential becomes uniform. Thus the boost word line system is employed, thereby difference of the read-out voltages of the memory cell can be eliminated.
The boost word line system is disclosed in "Fully Boosted 64K Dynamic RAM with Automatic and Self-Refresh" M. Taniguchi et al, IEEE Journal of Solid-State Circuits, SC-16, 492, 1981.
However, the boost word line system presents new problem. That is, as the semiconductor memory devices in recent years are more and more highly integrated and the short-channel effect of transistors increasingly becomes significant, the boost word line system becomes difficult to be employed. More specifically, in order to prevent the short-channel effect such as the drop in threshold voltage, the drop in breakdown voltage between the source and the drain and degradation of characteristics of the transfer gate transistor caused by a hot carrier effect, the substrate density of the semiconductor substrate further increases, and therefore lack of voltage withstand capability at the junction portion of the circuit generating high voltage becomes significant. Consequently, a system to eliminate the difference data read-out voltages described above without employing the boost word line system is desired.